World's First 0.2nm Microchip and the Secret Giant Behind It

Key Concepts:

• Moore's Law, Transistors, FinFET, Gate-All-Around (Nanosheet), CFET, Backside Power Delivery, Lithography (EUV, High NA EUV, Hyper Extreme EUV), 2D Materials (MoS2, WS2), CNTs (Carbon Nanotubes), CMOS 2.0, SRAM, DRAM, NAND, Memory Wall.

I. The Evolution of Transistors and Moore's Law

• Moore's Law, despite repeated declarations of its demise, is still relevant. Advancements are pushing chip technology to 2nm and beyond.
• The transistor is the fundamental building block of modern computing, powering devices from phones to AI systems.
• Tech giants like NVIDIA, Google, and Apple are developing custom chips, indicating a focus on chip-level innovation.
• NVIDIA's Blackwell GPU has 208 billion transistors, while the upcoming Rubin platform aims for 1.3 quadrillion transistors per server.
• AI capabilities are doubling roughly every 7 months (3.4x per year), while hardware performance only improves by 1.4x per year, creating a performance gap.
• Advancements occur at the device, architecture, and system levels, with the transistor as the foundation.
• IMEC innovates transistor technologies, which TSMC then manufactures at scale.
• IMEC's roadmap projects scaling from 2nm to 0.2nm by 2037 and beyond by 2039.

II. From FinFET to Gate-All-Around (Nanosheet)

• Current chips (AMD GPU, Apple Silicon) use FinFET technology.
• Planar transistors, used in the past, were simple 2D structures.
• FinFET transistors feature a vertical "fin" channel, improving current control and density compared to Planar transistors.
• The industry is transitioning from FinFET to Gate-All-Around (GAA) or Nanosheet technology.
• TSMC will introduce GAA technology in AMD and Apple chips by the end of the year.
• GAA transistors wrap the gate around all four sides of the channel, providing better control at smaller scales.
• Manufacturing challenges for GAA include the inability to directly see the underside of nanosheets; Applied Materials and ASM have solutions for this.
• TSMC's N3 process (3nm) packs 200 million transistors per square mm, while N2 (2nm) packs 300 million transistors per square mm.

III. Backside Power Delivery

• GAA technology introduces backside power delivery, moving power and signaling wires from the top of the chip to the backside.
• This frees up space on the top for interconnecting logic gates.
• TSMC and Intel are developing backside power delivery architectures.
• This technology will power devices from phones to advanced AI systems starting next year.

IV. CFET Architecture and Scaling Limits

• GAA technology is expected to reach its scaling limit around 1nm (10 Ångströms).
• The next major innovation is CFET (Complementary FET) architecture, which stacks GAA devices vertically.
• CFET allows for further footprint reduction and scaling to single Ångström dimensions.
• Challenges include bringing in the signal for the bottom device in the stack.

V. The Role of AI in the Workflow

• AI is transforming how people work, saving time and reducing costs.
• In 2025, over half of all companies are expected to use AI in some form.
• While 40% of people worry about AI replacing their jobs, those who use AI will likely replace those who don't.
• Microsoft, Google, and Amazon are hiring AI-skilled professionals.
• AI is a leverage for building startups, creating content, and improving professional work.

VI. Lithography Advancements

• Lithography tools are crucial for shrinking metal wires (interconnects) as transistors become smaller.
• The industry is developing High NA EUV (Extreme Ultraviolet) lithography tools with a numerical aperture of 0.55 for higher resolution.
• ASML has built and tested High NA EUV machines.
• Progress in lithography tools enables scaling of the metal pitch.
• The numbers 0.33, 0.55, and 0.75 refer to the numerical aperture of lithography tools, with higher numbers indicating better resolution.
• Older lithography tools enable scaling down to 22nm metal pitch, while 0.55 NA EUV tools are needed below that.
• Hyper Extreme EUV lithography will unlock the next milestone in semiconductors.

VII. 2D Materials and Beyond Silicon

• 2DFET uses 2D materials in the channel, with materials just one atom thick.
• 2D materials are considered the "end game" in semiconductors.
• Molybdenum disulfide (MoS2) and tungsten disulfide (WS2) are promising 2D materials.
• Building 2D materials at scale is challenging due to their thinness and fragility.
• Challenges include wrapping the gate around the channel when the channel is only one atom thick and preventing misalignment during manufacturing.
• The transition from GAA to CFET is more complex than the transition from FinFET to GAA.

VIII. Carbon Nanotubes (CNTs) and CMOS 2.0

• CNTs are rolled-up sheets of graphene and are being explored by IMEC and TSMC.
• Graphene offers high speed and current at low voltages, improving power efficiency.
• CNTs are difficult to turn off, leading to power leakage when idle.
• CMOS 2.0 is a new way of building chips by dividing them into different layers, each with a specific job.
• Different technologies and materials can be used for different layers (e.g., one for AI, another for graphics).

IX. Memory Bottleneck

• Memory is becoming the biggest bottleneck in today's systems.
• SRAM (for cache) does not scale well with new architectures like GAA.
• CFET architecture fits SRAM layouts well and provides a density jump.
• DRAM (for working memory) scales slowly, and 3D stacking is being used.
• Compute performance is improving faster than memory performance, leading to a "memory wall."

X. Implications for NVIDIA, Investors, and the Future

• Chip manufacturing is becoming more complex and expensive.
• While transistor costs may remain flat, wafer costs are increasing.
• Healthy competition between TSMC, Samsung, and Intel is crucial for progress.
• Increased complexity creates investment opportunities in the semiconductor space.
• Key players to watch include TSMC, ASML, and Applied Materials.

XI. Conclusion

The video provides a detailed look into the future of chip technology, highlighting the advancements in transistor design, lithography, materials, and memory. It emphasizes the challenges and opportunities in the semiconductor industry, particularly for companies like NVIDIA and investors. The transition from FinFET to GAA to CFET, along with the exploration of new materials like 2D materials and CNTs, promises to drive further innovation and performance improvements in computing. The memory wall remains a significant challenge, requiring new approaches to memory design and integration.