Programmable Logic Array (PLA) | Easy Explanation

Programmable Logic Array (PLA) Explained

Key Concepts:

• PLA (Programmable Logic Array): A type of fixed architecture programmable logic device (PLD) with programmable AND gates followed by programmable OR gates.
• Fixed Architecture Logic Device/PLD: A logic device with a predefined structure that can be programmed to implement different logic functions.
• Programmable AND Gate: An AND gate where the inputs can be selectively connected to input variables or their complements.
• Programmable OR Gate: An OR gate where the inputs can be selectively connected to the outputs of AND gates.
• Minimal SOP (Sum of Products) Form: A simplified Boolean expression representing a logic function as a sum of product terms.
• Input Buffer: A combination of NOT gates that provides both the normal and complemented forms of input variables.
• Minterm: A product term in a Boolean expression that includes all input variables, either in their normal or complemented form.

Step-by-Step PLA Implementation

The presentation outlines a step-by-step process for implementing a logic function using a PLA, illustrated with an example truth table.

1. Truth Table:

• The starting point is a truth table that defines the desired logic functions.
• Example: A truth table with inputs A, B, and C, and outputs Y1 and Y2.

2. Minimal SOP Form:

• Derive the minimal Sum of Products (SOP) form for each output function (Y1, Y2) using Boolean algebra or Karnaugh maps (K-maps).
• Example:
  • Y1 = A * B' * C' + A * B' * C + A * B * C => A * B' + A * C
  • Y2 = B * C + A * C

3. Input Buffers:

• Determine the number of input buffers required. The number of input buffers equals the number of input variables.
• Create input buffers for each variable to provide both the normal and complemented forms (A, A', B, B', C, C').
• The input buffer is implemented using two NOT gates in series, where the input and the output of the first NOT gate provide the normal and complemented forms of the input variable, respectively.
• Example: With inputs A, B, and C, three input buffers are needed.

4. Programmable AND Gates:

• Determine the number of programmable AND gates. This equals the number of unique minterms in the minimal SOP forms of all output functions. Repeated minterms are counted only once.
• Example: Y1 = A * B' + A * C and Y2 = B * C + A * C has three unique minterms: A * B', A * C, and B * C. Therefore, three AND gates are required.
• Draw the required number of AND gates.
• Connect the inputs of each AND gate to the appropriate input variables or their complements based on the corresponding minterm. A cross (X) at the intersection of a variable line and an AND gate input line indicates a connection.
• Example:
  • AND gate 1: Connected to A and B' to implement A * B'.
  • AND gate 2: Connected to A and C to implement A * C.
  • AND gate 3: Connected to B and C to implement B * C.

5. Programmable OR Gates:

• Determine the number of programmable OR gates. This equals the number of output functions.
• Example: Two OR gates are needed for Y1 and Y2.
• Draw the required number of OR gates.
• Connect the inputs of each OR gate to the outputs of the AND gates that correspond to the minterms in the SOP form of the respective output function.
• Example:
  • OR gate 1 (Y1): Connected to the outputs of AND gate 1 (A * B') and AND gate 2 (A * C).
  • OR gate 2 (Y2): Connected to the outputs of AND gate 3 (B * C) and AND gate 2 (A * C).

Advantages of PLA

• Portability: PLAs offer a more portable solution for implementing combinational logic compared to traditional gate-and-wire implementations.
• Programmability: PLAs can be easily programmed to implement different Boolean functions.
• Chip-Based Implementation: PLAs are available as chips, allowing for easy integration into digital systems.

Conclusion

The PLA provides a structured and programmable way to implement combinational logic functions. By following the outlined steps, one can design a PLA to realize a given set of Boolean equations. The PLA's programmability and portability make it a valuable tool in digital circuit design. The next presentation will discuss the Programmable Array Logic (PAL).