CO29 - Single Bus Organization Processor | Instruction Fetch

Single Internal Bus Processor

Key Concepts: Single internal bus, program counter (PC), memory address register (MAR), memory data register (MDR), arithmetic logic unit (ALU), instruction register (IR), decoder and control logic, temporary registers (Y, Z, Temp), control signals (e.g., PC out, MAR in), instruction fetch cycle.

Processor Architecture

The lecture focuses on a processor design featuring a single internal bus. This bus connects various components within the microprocessor, facilitating data transfer between them. The components include:

• Program Counter (PC): Stores the address of the next instruction to be executed. Connected to the internal bus.
• Memory Address Register (MAR): Holds the memory address to be accessed. Receives input from the internal bus and connects to the external address bus.
• Memory Data Register (MDR): Acts as a buffer for data being read from or written to memory. Connected to both the internal and external data buses, with bidirectional data flow.
• ALU: Performs arithmetic and logical operations.
• General Purpose Registers (R0 to RN-1): A set of registers for storing data. Connected to the internal bus.
• Instruction Register (IR): Holds the instruction currently being executed. Receives input from the internal bus and passes it to the decoder and control logic.
• Decoder and Control Logic: Decodes the instruction in the IR and generates the appropriate control signals.
• Temporary Registers (Y, Z, Temp): Used for temporary storage of data during operations. Y is connected to a multiplexer. Z stores the ALU output.

The architecture also includes a multiplexer that selects between a constant value of 4 and the contents of the Y register as input to the ALU. The ALU's output is stored in the Z register.

Single Bus Constraint and Control Signals

A key constraint of this architecture is that only one unit can output data onto the internal bus at any given time (in a single clock cycle). However, multiple units can simultaneously receive data from the bus.

To manage data flow on the bus, each unit has associated control signals:

• R0 in: Enables data to be received from the bus into register R0.
• R0 out: Enables the contents of register R0 to be output onto the bus.
• Y in: Enables data to be received from the bus into register Y.
• Z in: Enables the result of the ALU computation to be stored in register Z.
• Z out: Enables the contents of register Z to be output onto the internal bus.

These control signals are essential for coordinating data transfer and preventing conflicts on the single internal bus.

Constant 4 and Multiplexer

The constant 4 input to the multiplexer is used to increment the program counter (PC) by 4, assuming each instruction is 4 bytes long and the memory is byte-addressable. If the memory were word-addressable, this constant would be 1.

The multiplexer selects either the constant 4 or the contents of the Y register to be passed to the ALU, based on the Select 4 or Select Y control signal.

ALU Control Signals

The ALU's operations are controlled by a set of control signals. If the ALU can perform 16 operations, it can be controlled by 16 individual control lines (one for each operation) or by an encoded set of 4 control lines, where each combination of the 4 lines specifies a particular operation.

Instruction Fetch Control Sequence

The lecture details the control sequence for the instruction fetch cycle:

1. PC out: The contents of the PC are placed onto the internal bus.
2. MAR in: The contents of the bus (the address from the PC) are loaded into the MAR. Simultaneously, the address is sent to the external address bus, and a read control signal is sent to memory.
3. Select 4 and Z in: The constant 4 is selected via the multiplexer, added to the PC's value (which is already on the bus), and the result (PC + 4) is stored in the Z register.
4. Z out: The contents of the Z register (PC + 4) are placed onto the internal bus.
5. PC in and Y in: The updated address (PC + 4) is loaded back into the PC and also stored in the temporary register Y.
6. WMFC (Wait for Memory Function Complete): The processor waits for the memory to complete its read operation and send back the instruction. This signal is crucial because memory access time can vary (e.g., cache hit vs. main memory access).
7. MDR in external: Once the memory function is complete, the instruction is loaded into the MDR from the external data bus.
8. MDR out: The instruction is placed onto the internal bus from the MDR.
9. IR in: The instruction is loaded into the instruction register (IR).

After the instruction fetch cycle, the instruction is available in the IR and ready for decoding and execution. The value in Y is available for use in subsequent operations if needed.

Conclusion

The lecture provides a detailed explanation of a single internal bus processor architecture, highlighting its components, constraints, and control mechanisms. The instruction fetch cycle is presented as a concrete example of how these components and control signals work together to execute a fundamental processor operation. The single bus architecture simplifies design but introduces constraints on data transfer, necessitating careful control signal management.