Basics of VERILOG | Datatypes, Hardware Description Language, Reg, Wire, Tri, Net, Syntax | Class-1

Key Concepts

• System: A circuit with inputs and outputs that performs operations.
• Hardware Description Language (HDL): A language used to describe the behavior and structure of digital circuits.
• Verilog HDL: A specific HDL used for digital circuit design and verification.
• Abstraction Levels: Different methods or levels of detail used to describe a circuit in Verilog (Behavioral, Data Flow, Gate Level, Switch Level).
• Module: The fundamental building block in Verilog, encapsulating a design.
• Ports: Input and output signals of a module.
• Identifiers: Names given to modules, variables, and other elements in Verilog code.
• Case Sensitivity: Verilog distinguishes between uppercase and lowercase letters in identifiers.
• Comments: Explanatory notes in the code that improve readability.
• Data Types: Categories of variables that define the type of data they can store (e.g., net, register, integer).
• Nets: Data types that represent physical connections and must be continuously driven.
• Registers: Data types that store values and retain them until updated.
• Vectors: Multi-bit variables represented as arrays.

Verilog Introduction and Fundamentals

The discussion begins with the fundamental question of why Verilog is used. The core concept is that a system takes inputs, processes them using a circuit, and produces outputs. Verilog, a Hardware Description Language (HDL), provides instructions to the circuitry to define its behavior. Two primary HDLs are Verilog HDL and VHDL. Verilog was initially introduced by Gateway Automation, later acquired by Cadence Design Systems.

Abstraction Levels in Verilog

Verilog offers different levels of abstraction for coding, allowing designers to choose the most suitable approach based on their requirements. These levels include:

• Behavioral Level: Describes the what (functionality) of a circuit without specifying the how (implementation).
• Data Flow Level: Describes the circuit using data flow equations and assignments.
• Gate Level: Describes the circuit using logic gates (AND, OR, NOT, etc.).
• Switch Level: Describes the circuit using transistors and switches.

Verilog vs. Software Languages (C)

While Verilog resembles software languages like C, a key difference is that Verilog is synthesizable. This means Verilog code can be translated into a physical hardware implementation. Additionally, Verilog supports concurrent execution of instructions, unlike the sequential execution in C.

Basic Verilog Syntax

The basic structure of a Verilog program involves:

1. Module Declaration: Begins with the module keyword and ends with endmodule.
2. Port Declaration: Specifies the input and output ports of the module within the module declaration. Semicolon termination is crucial.
3. Input/Output Declaration: Declares which ports are inputs and which are outputs.
4. Logic Implementation: Contains the code that defines the circuit's behavior or structure.

Identifiers

Identifiers are names given to modules, variables, and other elements. They must follow specific rules:

• Case-sensitive (e.g., count, Count, and COUNT are different).
• Cannot start with a special symbol (except underscore _).
• Cannot start with a numeral.
• Spaces are not allowed.

Valid identifiers: _count, count1, count_1, $count (only dollar sign allowed). Invalid identifiers: $1count, 1count, count#, count 1.

Comments

Comments improve code readability. Verilog supports two types of comments:

• Short Comments: Use // for single-line comments.
• Long Comments: Use /* ... */ for multi-line comments.

White Spaces

Verilog ignores extra spaces, tabs, and blank lines. However, using proper indentation and line breaks enhances readability.

Behavioral Modeling

Behavioral modeling focuses on what the circuit does. Key aspects include:

• Using procedural statements within an always block.
• The always block is triggered by changes in the sensitivity list.
• Variables assigned values within an always block must be of reg type.
• Example:

module and_gate (input a, b, output reg y);
  always @(a or b) begin
    y = a & b;
  end
endmodule

In this example, y is declared as reg because it's assigned a value inside the always block. The always block is sensitive to changes in a or b.

Data Flow Modeling

Data flow modeling describes the circuit using assign statements. Key aspects include:

• Using the assign keyword to assign values to signals based on expressions.
• Suitable for describing combinational logic.
• Can use predefined gates from Verilog libraries.
• Example:

module and_gate (input a, b, output y);
  assign y = a & b;
endmodule

Here, the assign statement directly assigns the result of a & b to y.

Gate Level Modeling

Gate-level modeling involves instantiating primitive gates (AND, OR, NOT, etc.) to describe the circuit's structure. Predefined gates are available in Verilog libraries.

Switch Level Modeling

Switch-level modeling describes the circuit using transistors and switches.

Data Types in Verilog

Data types define the kind of values a variable can hold. Two main categories are:

• Net Data Types: Represent physical connections and must be continuously driven. Examples include wire, tri, wand, wor, supply0, and supply1.
• Register Data Types: Store values. Examples include reg, integer, real, and time.

Net Data Types

• wire: The most common net type, representing a simple connection.
• wand and wor: Used when multiple drivers drive a single net. wand (wired-AND) results in a high (1) only if all drivers are high. wor (wired-OR) results in a high if any driver is high.
• tri: Used for tri-state buffers.
• supply0: Represents ground (logic 0).
• supply1: Represents power (logic 1).

Register Data Types

• reg: A basic register type used to store values in procedural blocks.
• integer: A 32-bit signed integer.
• real: A floating-point number.
• time: Stores simulation time.

Vectors

Vectors are multi-bit variables declared using a range:

wire [7:0] data; // 8-bit wire
reg [31:0] address; // 32-bit register

The range specifies the most significant bit (MSB) and least significant bit (LSB). Individual bits or parts of the vector can be accessed using indexing:

data[0] // LSB of data
address[31:16] // Upper 16 bits of address

Using Parts of Arrays

It's possible to assign parts of one vector to another:

wire [7:0] x;
wire [3:0] y;
assign y = x[7:4]; // Assigns bits 7-4 of x to y

Synthesis/Conclusion

The lecture provides a foundational understanding of Verilog HDL, covering its purpose, syntax, abstraction levels, data types, and basic modeling techniques. It emphasizes the differences between behavioral and data flow modeling, the importance of data types, and the use of vectors for multi-bit signals. The concepts presented are essential for designing and verifying digital circuits using Verilog.